Question
Download Solution PDFThe minimum number of 2-input NAND gates required to realise sum and carry of a half adder
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFSum expression of a half adder is given by:
Sum = A XOR B = \(\bar A\;B + A\;\bar B\)
The implementation of half adder circuit is shown below:
We can conclude that to generate the sum bit, we only need 4 NAND gates.
|
Logic Gates |
Min. number of NOR Gate |
Min. number of NAND Gate |
|
NOT |
1 |
1 |
|
AND |
3 |
2 |
|
OR |
2 |
3 |
|
EX-OR |
5 |
4 |
|
EXNOR |
4 |
5 |
|
NAND |
4 |
1 |
|
NOR |
1 |
4 |
|
Half-Adder |
5 |
5 |
|
Half-Subtractor |
5 |
5 |
|
Full-Adder |
9 |
9 |
|
Full-Subtractor |
9 |
9 |
Last updated on May 30, 2025
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