The resolution of a dual slope ADC can be increased by

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VSSC ISRO Technical Assistant Electronics 8 Feb 2015 Official Paper
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  1. Increasing the reference voltage magnitude
  2. Improving the reference voltage accuracy
  3. Increasing the clock frequency
  4. Increasing the clock stability

Answer (Detailed Solution Below)

Option 3 : Increasing the clock frequency
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The resolution of the dual-slope ADC is determined by the length of the run-down period and by the time measurement resolution (i.e., the frequency of the controller's clock).

The resolution (in the number of bits) is the minimum length of the run-down period for a full-scale input(Vin = - Vref).

\({t_d} = \frac{{{2^r}}}{{{f_{clk}}}}\)

Where td is the run-down period,

r is resolution

fclk is the frequency of the clock.

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IMPORTANT POINT:

There are limits to the maximum resolution of the dual-slope integrating ADC. It is not possible to increase the resolution of the basic dual-slope ADC to arbitrarily high values by using longer measurement times or faster clocks. 

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