Machine Instructions and Addressing Modes MCQ Quiz in मल्याळम - Objective Question with Answer for Machine Instructions and Addressing Modes - സൗജന്യ PDF ഡൗൺലോഡ് ചെയ്യുക
Last updated on Mar 9, 2025
Latest Machine Instructions and Addressing Modes MCQ Objective Questions
Top Machine Instructions and Addressing Modes MCQ Objective Questions
Machine Instructions and Addressing Modes Question 1:
In X = (M + N × O) / (P × Q), how many one-address instructions are required to evaluate it?
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 1 Detailed Solution
The correct answer is "option 3".
CONCEPT:
To obtain operand value from memory, the address field of an instruction is used by the CPU.
In single address instruction, one of the operands is stored in the accumulator & the other operand may be either in register or memory.
EXPLANATION:
All the operations will be performed in the Accumulator register(AC).
The load operation is used to fetch the value from register or memory to accumulator.
The store operation is used to store the value from the accumulator to register or memory.
The one address instructions for the given equations are:
Load/Store/Operation |
One-address Instruction |
LOAD N | AC ← M[N] |
MUL O | AC ← AC × M[O] |
ADD M | AC ← AC + M[M] |
STORE T | M[T] ← AC |
LOAD P |
AC ← M[P] |
MUL Q |
AC ← AC × M[Q] |
DIV T |
AC ← AC/ M[T] |
STORE X |
M[X] ← AC |
Hence, the correct answer is "option 3".
Machine Instructions and Addressing Modes Question 2:
The following language uses mnemonic OP codes
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 2 Detailed Solution
In assembly language mnemonics are used to represent operation codes.
Opcodes (operation codes) are represented by abbreviations, called mnemonics that indicate the operation.
Mnemonic codes:
- Mnemonic codes are the codes that can be remembered comparatively easily and that aids its user in recalling the information it represents.
- Mnemonics codes are widely used in computer programming and communication system operations to specify instructions.
Examples:
ADD Add
SUB Subtract
MUL Multiply
DIV Divide
LOAD Load data from memory
STOR Store data to memory
Assembly language: It is a low-level programming language that uses symbols, variables, and functions that work directly with CPU.
High-level language: It is a human-friendly language that uses variables and functions, independent of the computer architecture.
Assembly language |
High-level language |
Programs written for one processor will not run on other types of processors. |
The program runs independently on process type. |
Performance and accuracy are better than high-level lang. |
Performance & accuracy are lesser. |
Executable code is less than high-level lang., takes less time to execute & program runs faster |
Executable code is larger, takes a long time to execute. |
Eg.: ARM, MIPS |
Eg.: C, C++, JavaScript |
Machine Instructions and Addressing Modes Question 3:
Consider a processor with 28 registers and an instruction set of size 35. Each instruction has four distinct fields, namely, opcode, one source register identifiers, one destination register identifier, and a sixteen-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 2000 instructions, the amount of memory consumed by the program text is ______ KB. (1 K = 103)
Answer (Detailed Solution Below) 8
Machine Instructions and Addressing Modes Question 3 Detailed Solution
Data:
Number of registers = 28
Number of instructions = 35
Formula:
Number of bits =⌈ log2N ⌉
Calculation:
Number of bits to address register = ⌈ log2 28 ⌉ = 5
Opcode size = ⌈ log2 35 ⌉ = 6 bits
source register = destination register = 5 bits
Opcode |
Source Register |
Destination register |
Immediate |
6 bits |
5 bits |
5 bits |
16 bits |
Total bits per instruction = 6 + 5 + 5 + 16 = 32 bits
In terms of bytes= \(\frac{{32}}{8}\)= 4 bytes
Total instructions = 2000
Total size = 2000 × 4 = 8000 bytes = 8 KBMachine Instructions and Addressing Modes Question 4:
If a basic instruction format instruction set includes ADD, SUB, LDA, STA, CLR as its opcode then what is the minimum number of bits needed for opcode?
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 4 Detailed Solution
Instruction set: ADD, SUB, LDA, STA, CLR
There are 5 opcodes possible at any time within an instruction. Hence each opcode needs to denote with a unique binary sequence.
Consider the below table:
Opcode |
Corresponding binary sequence |
ADD |
000 |
SUB |
001 |
LDA |
010 |
STA |
011 |
CLR |
100 |
Therefore minimum 3 bits is needed for opcode.
Shortcuts:
Number of opcodes = n
Number of bits needed in opcode = ⌈ log2n ⌉ = ⌈ log25 ⌉ = 3Machine Instructions and Addressing Modes Question 5:
Assume an instruction set that uses a fixed 20-bit instruction length. Operand specifiers are 6 bits in length. There are K two-operand instructions and no zero-operand instructions. What is the maximum number of one-operand instructions that can be supported?
Answer (Detailed Solution Below)
214 – 26 K
Machine Instructions and Addressing Modes Question 5 Detailed Solution
Data:
Instruction length = 20 bits
Total address possible = 220
Operand specifiers = 6 bits
0 – address = 0
1 – address = y × 26
2 – address = K × 26 × 26= 212 K
Formula:
0 – address + 1 – address + 2 – address ≤ Total Address
Calculation:
0 + y× 26 + 212 K ≤ 220
y ≤ 214 – 26 K
ymax = 214 – 26 K
∴ option 1 is correct
Machine Instructions and Addressing Modes Question 6:
Zero address instruction format is used for
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 6 Detailed Solution
The correct answer is option 4:
Key Points
In stack organized architecture push and pop instruction is needs a address field to specify the location of data for pushing into the stack and destination location during pop operation but for logic and arithmetic operation the instruction does not need any address field as it operates on the top two data available in the stack.
Machine Instructions and Addressing Modes Question 7:
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is ______.
Answer (Detailed Solution Below) 14
Machine Instructions and Addressing Modes Question 7 Detailed Solution
Data:
Instruction length = 16 bits
Number of registers = 64
Bits to represent register = ⌈ log2 (64) ⌉ = 6
Explanation
I-type instruction format:
Opcode |
Register 6 bits |
Immediate Value 4 bits |
R-type instruction format =
Opcode |
Register 6 bits |
Register 6 bits |
Instruction length is given 16, therefore maximum possible encodings = 216
Number of I-type opcodes = 8
I-type Instructions encoding + R-type instructions encoding = Total instructions
Assume the number of R-type opcodes = x
Therefore,
(8 × 26 × 24) + (x × 26 × 26) = 216
÷ b 212 on both side
∴ 2 + x = 24
∴ x = 14.
Machine Instructions and Addressing Modes Question 8:
Which of the following statements is/are true?
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 8 Detailed Solution
The correct answer is option 1, option 3 and option 4.
Concept:
Option 1: In the immediate addressing mode the operand is placed in the instruction itself.
True, An immediate mode instruction has an operand field rather than an address field. The operand field contains the actual operand to be used in conjunction with the operation specified in the instruction.
Option 2: One-byte machine instruction consists of the only operand.
False, The machine instructions which consist of the only opcode are called one-byte machine instructions.
Option 3: Indirect addressing mode is suitable for implementing pointers in C.
True, Indirect addressing mode is suitable for implementing pointers in C. The instruction includes the address of the place where the target address is stored in this style of addressing. As a result, it is indirectly storing the target site's address in another memory location.
Option 4: Displacement addressing mode is similar to the register indirect addressing mode.
True, The displacement addressing mode is equal to the register indirect addressing mode, with the exception that the effective address of the operand is formed by adding an offset (or displacement) maintained in the instruction to the contents of the register provided in the instruction.
Hence the correct answer is option 1, option 3 and option 4.
Machine Instructions and Addressing Modes Question 9:
When CPU is executing a Program that is part of the Operating System, it is said to be in
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 9 Detailed Solution
CPU will pick a program from the ready queue maintained by Operating System and will start executing it. At that time it is said to be in system mode because it is executing the normal program for the system.
In case if interrupt comes in between then after executing the current process(high priority) CPU will search for the interrupt to execute.
The interrupt is a signal emitted by hardware or software when a process or an event needs immediate attention.
Let's analyze the options one by one-
Option 1-When CPU will service the interrupt request at that time it is said to be in interrupt mode.
Option 2- This is the correct answer as explained above.
Option 3- There is nothing called "Half mode " in operating system execution.
Option 4- Simplex mode is a concept in Computer Network where the communication between sender and receiver occur only in one direction.
Machine Instructions and Addressing Modes Question 10:
Consider that following program segment for a hypothetical CPU having two user registers R1 and R2.
Instruction |
Operation |
Instruction size (in words) |
MOV R1, M[2500] |
R1 ← Memory[2500] |
2 |
MOV R2, #10 |
R2 ← R2 + 10 |
1 |
ADD R1, R2 |
R1 ← R1 + R2 |
2 |
HALT |
Machine halts |
1 |
Consider that the memory is byte addressable with size 64 bits and program has been loaded from memory location 2000(decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack.
Answer (Detailed Solution Below)
Machine Instructions and Addressing Modes Question 10 Detailed Solution
The correct answer is option 2.
Concept:
The given data,
Physical Address = 64 bit and it is byte-addressable
1 Word = 64 bit = 8 bytes
2 word = 128 bit = 16 bytes
Base location = 2000
Instruction |
Starting address |
Ending address |
Explanation |
I1 |
2000 |
2015 |
Here moving the M[2500] to R1. The instruction size is 2 bytes=16 bits so it is saved from 2000 to 2015. |
I2 |
2016 |
2023 |
It moves the value 10 to the R2 register. The instruction size is 1 byte=8 bit so it is saved from 2016 to 2023. |
I3 |
2024 |
2039 |
Adds both registers. The instruction size is 2 byte=16 bit so it is saved from 2024 to 2039. |
I4 |
2040 |
2047 |
Halts the code. The instruction size is 1 byte=8 bit so it is saved from 2040 to 2047 |
If an interrupt occurs the CPU has been halted after execution of the HALT instruction, the return address 2040 is saved in the stack.
Hence the correct answer is 2040.