Instruction Format MCQ Quiz in मराठी - Objective Question with Answer for Instruction Format - मोफत PDF डाउनलोड करा
Last updated on Mar 15, 2025
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Instruction Format Question 1:
A CPU has 19 registers and uses 10 addressing modes. RAM is 8K × 32. What is the maximum size of the op-code field if the instruction has a register operand and a memory address operand?
Answer (Detailed Solution Below)
Instruction Format Question 1 Detailed Solution
Data:
number of registers = 19
addessing mode = 10
RAM size = 8K × 32 = 213 × 25
Formula:
Memory Capacity is of the form = 2m × 2n
Address lines required = m
Instrcution size = Data Lines = 2n
number of bits = ⌈log2 n⌉
number of register or number addressing modes
Calculation:
Instrcution size = Data Lines = 32 bits
Address lines required = 13 bits
number of bits for a addressing mode = ⌈log2 10⌉ = 4
number of bits for a register field = ⌈log2 19⌉ = 5
|
Addressing Mode |
op-code field |
Register |
Memory Address field |
|
4 bits |
x bits |
5 bits |
13 bits |
4 + x + 5 + 13 = 32
∴ x = 10
op-code field = 10 bits
Instruction Format Question 2:
A micro instruction format has micro operation field which is divided into 2 subfields F1 and F2, each having 15 distinct microoperations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is:
Answer (Detailed Solution Below)
Instruction Format Question 2 Detailed Solution
Micro instruction format: It consists of two fields of micro-operation. One field from conditions, one for branch field and one is address field.
|
F1 |
F2 |
Condition |
Branch |
Address |
Explanation:
Micro operation field into two subfields containing 15 micro operations each.
Condition field: 4 status bits
Branch: 4 options in conjunction with address
So, bits required for microoperations = log215 + log215 = 4 + 4 = 8
Condition = log24 = 2
Branch in conjunction with address field = log2(4 × 128) = log2 512 = 9
|
F1 (4 bits) |
F2( 4 bits) |
Condition( 2 bits) |
Branch with address (9 bits) |
Size of micro – instruction = 8 + 2 + 9 = 19 bits
Instruction Format Question 3:
Which of the following register holds memory operand?
Answer (Detailed Solution Below)
Instruction Format Question 3 Detailed Solution
Instruction Format Question 4:
Consider a 32-bit processor which supports 30 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
Answer (Detailed Solution Below) 128
Instruction Format Question 4 Detailed Solution
Data:
Each instruction = 32 bit
Number of instructions which are supported = 30
Maximum value by unsigned operand = 8191
Formula:
|
Opcode |
Register 1 (R) |
Register 2 (R) |
Immediate Operand |
In bits,
Opcode + R + R + Immediate Operand = 32
Calculation
Number of bits needed for opcode = ⌈ log2(30)⌉ = 5 bits
The maximum value of unsigned immediate operand = 8191
2n – 1 = 8191
2n = 8192 = 213
∴ n = 13 bits
5 + R + R + 13 = 32
2R = 14
∴ R = 7 bits.
Maximum registers that a processor has = 27 = 128Instruction Format Question 5:
Consider a 32-bit processor that supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two-register identifiers, and an immediate operand. Maximum number of registers that a processor has is 64. Minimum value of the immediate operand that can be supported by the processor if the system uses 2's complement number system?
Answer (Detailed Solution Below) -4096
Instruction Format Question 5 Detailed Solution
Data:
Each instruction = 32 bit
Number of instructions which are supported = 70
Maximum number of register = 64
Formula:
|
Opcode |
Register 1 (R) |
Register 2 (R) |
Immediate Operand |
In bits,
Opcode + R + R + Immediate Operand = 32
Calculation
Number of bits needed for opcode = ⌈ log2(70)⌉ = 7 bits
Number of bits needed for register = ⌈ log2(64)⌉ = 6 bits
7 + 6 + 6 + x = 32
x = 13 bits
System is in 2's complement
Minimum value = -213-1 = -4096.Instruction Format Question 6:
In instruction, the operation is specified by a binary code, known as the __________.
Answer (Detailed Solution Below)
Instruction Format Question 6 Detailed Solution
Each instruction must contain the information required by the processor for execution.
Operation code: Specifies the operation to be performed (e.g., ADD, I/O). The operation is specified by a binary code, known as the operation code, or opcode.Instruction Format Question 7:
A processor has 256 distinct instructions. A 30-bit instruction word has an opcode, one register operand, and an immediate operand. The number of bits available for the immediate operand field is 15. The maximum number of register operand is _________.
Answer (Detailed Solution Below) 128
Instruction Format Question 7 Detailed Solution
Data:
Instruction size = 30 bits
Distinct instruction = 256
operand = 15 bits
Formula:
number of bits = ⌈log2n⌉
Calculation:
Number of bits needed for instruction = ⌈log2256⌉ = 8
Instruction format (30 bit):
|
Opcode(instruction) |
Register |
Operand |
|
8 bits |
x bits |
15 bits |
8 + x + 15 = 30
∴ x = 7
he maximum number of register operand is = 27 = 128
Instruction Format Question 8:
Only instructions with zero, one, and two addresses are supported by some CPUs. The size of an op-code is 16 bits, whereas the size of an address is 4 bits.
What is the Maximum number of two address instructions?
Answer (Detailed Solution Below) 256
Instruction Format Question 8 Detailed Solution
The correct answer is 256.
Concept:
Two Address Instructions:
Commercial computers frequently have this. Two addresses can be supplied in the instruction in this case. Instead of the result being saved in the accumulator as it was in prior address instructions, the result can now be stored in many locations, however, this requires extra bits to indicate the address.
Explanation:
The given data,
The CPU supports op-code size = 16 bits
Address size = 4 bits
We have two operands so it requires the 2 x 4 bits =8
And remaining 16-8 bits can be used for two address instructions.
i.e 8 bits.
Maximum number of instructions = 28 = 256
Hence the correct answer is 256.
Instruction Format Question 9:
Consider the following :
1) Operation code
2) Source operand reference
3) Result operand reference
4) Next instruction reference
Which of the above are typical elements of machine instructions?
Answer (Detailed Solution Below)
Instruction Format Question 9 Detailed Solution
All Operation code, Source operand reference, Result operand reference, and Next instruction reference are typical elements of machine instructions.
Operation code: Operation Code is the Code that is used to specifies the operation that will be going to be performed. This code is also in the form of binary numbers and it is known as an opcode.
Source operand reference: Source Operand reference are the inputs for the process and it will be one or more than one operation.
Result operand reference: Result Operand Reference produces a result.
Next instruction reference: Next instruction reference tells the processor where to send the next instruction.
Instruction Format Question 10:
In a computer, a memory unit is of size 256 KW where W stands for word. Word size is 32 bits. The instruction has four parts: addressing mode, operation code, register code and address part. An addressing mode part is used to specify one of two-addressing mode (direct or indirect). Register code part is used to specify one of the 64 registers. How many bits are there in addressing mode part, opcode part, register code part, and the address part?
Answer (Detailed Solution Below)
Instruction Format Question 10 Detailed Solution
Data:
Memory unit = 256 KW = 218 W
1 word = 32 bits = 4 B
Binary instruction code stored in 1 word of memory
Instruction divided as follows,
| addressing mode | operation mode | register code | address |
| 1 bit | x bits | 6 bits | 18 bits |
Calculation:
Addressing mode = 1 bit for direct or indirect
Register code = ln (64) = 6 bits
Since registers are already addressed, only memory needs to be addressed
Address part = ln (218) = 18 bits
Operation mode = 32 – 1 – 6 – 18 = 7 bits
Therefore, bits for addressing mode part, opcode part, register code part and the address part = (1, 7, 6, 18)